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Dec. 2006
HY[B/E]25L256160AC HY[B/E]25L256160AF
DRAMs for Mobile Applications 256-MBit Mobile-RAM R oH S c o mp l i a nt
Internet Data Sheet
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HY[B/E]25L256160A[F/C]-7.5 256MBit Mobile-RAM
HY[B/E]25L256160AC, HY[B/E]25L256160AF Revision History: 2006-12, Rev. 1.41 Page All All All 9 2 Subjects (major changes since last revision) Adapted internet edition New Qimonda Template Added new Product Type VDD: editorial change Added disclaimer
Previous Revision: 2005-06, Rev. 1.4
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com Internet Data Sheet 2 Rev. 1.41, 2006-12 04292004-EQNL-FLNW
HY[B/E]25L256160A[F/C]-7.5 256MBit Mobile-RAM
Overview
1
1.1
* * * * * * * * * * * * * * * * * * * * * *
Overview
Features
16 Mbits x 16 organisation Fully synchronous to positive clock edge Four internal banks for concurrent operation Data mask (DM) for byte control with write and read data Programmable CAS latency: 2 or 3 Programmable burst length: 1, 2, 4, 8, or full page Programmable wrap sequence: sequential or interleaved Random column address every clock cycle (1-N rule) Deep power down mode Extended mode register for Mobile-RAM features Temperature compensated self refresh with on-die temperature sensor Partial array self refresh Power down and clock suspend mode Automatic and controlled precharge command Auto refresh mode (CBR) 8192 refresh cycles / 64 ms Self-refresh with programmble refresh period Programmable power reduction feature by partial array activation during self-refresh VDDQ = 1.8V or 2.5 V or 3.3 V VDD = 2.5 V or 3.3 V P-TFBGA-54 package 9-by-6-ball array with 3 depopulated rows (12 x 8 mm2) Operating temperature range: commercial (0 C to +70 C) extended (-25 C to +85 C) Performance 1) -7.5 @CL3 @CL3 @CL3 @CL2 @CL2 Unit MHz ns ns ns ns
Table 1
Part Number Speed Code max. Clock Frequency min. Clock Period min. Access Time from Clock min. Clock Period min. Access Time from Clock
fCK3 tCK3 tAC3 tCK2 tAC2
133 7.5 6.0 9.5 6.0
1) for VDDQ = 2.5 V or 3.3 V; see Table 9 for VDDQ dependent performance
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HY[B/E]25L256160A[F/C]-7.5 256MBit Mobile-RAM
Overview
1.2
Description
The 256MBit Mobile-RAM is a new generation of low power, four bank synchronous DRAM organized as 4 banks x 4 Mbit x 16 with additional features for mobile applications. The synchronous Mobile-RAM achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The device adds new features to the industry standards set for synchronous DRAM products. Parts of the memory array can be selected for Self-Refresh and the refresh period during Self-Refresh is programmable in 4 steps which drastically reduces the self refresh current, depending on the case temperature of the components in the system application. In addition a "Deep Power Down Mode" is available. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. The Mobile-RAM is housed in a FBGA "chip-size" package. The Mobile-RAM is available in the commercial (0 C TC 70 C) and extended (-25 C to +85 C) temperature range.
Table 2
Ordering Information for Non-Green Products Function Code PC133-333-522 PC133-333-522 Case Temperature Range commercial (0 C TC 70 C) extended (-25 C to +85 C) Package P-TFBGA-54 P-TFBGA-54
Product Type1) HYB25L256160AC-7.5 HYE25L256160AC-7.5 Table 3
Ordering Information for Green Products Function Code PC133-333-522 PC133-333-522 Case Temperature Range commercial (0 C TC 70 C) extended (-25 C to +85 C) Package P-TFBGA-54 P-TFBGA-54
Product Type1) HYB25L256160AF-7.5 HYE25L256160AF-7.5
1) HYB/E: designator for memory components for commercial /extended temperature range 25L: Mobile-RAM at VDD = 2.5 V 256: 256-Mbit density 160: Product variation x16 A: Die revision A F/C: Lead & Halogen free / Lead-Containing -7.5: speed grade - see Table 1
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Pin Configuration
2
Pin Configuration
1 VSS DQ14 DQ12 DQ10 DQ8 UDQM A12 A8 VSS
2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5
3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 A B C D E F G H J
7 VDDQ VSSQ VDDQ VSSQ VDD CAS BA0 A0 A3
8 DQ0 DQ2 DQ4 DQ6 LDQM RAS BA1 A1 A2
9 VDD DQ1 DQ3 DQ5 DQ7 WE CS A10/AP VDD
< Top-view >
Figure 1
Pin Configuration P-TFBGA-54 (16 Mb x 16)
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Pin Configuration Table 4 F2 F3 CLK CKE Input/Output Signals Polarity Function Positive Clock Edge Active High Active Low Active Low Active High Active High Clock Enable Chip Select Command Inputs Input Input Input Input
Pin Symbol Type
G9 CS F8 F7 F9 RAS CAS WE
G8 BA1 G7 BA0 G1 A12 G2 A11 H9 A10/AP G3 A9 H1 A8 H2 A7 H3 A6 J2 J3 J7 J8 A5 A4 A3 A2
Input Input
Bank Address Inputs Address Inputs
H8 A1 H7 A0 A2 DQ15 B1 DQ14 B2 DQ13 C1 DQ12 C2 DQ11 D1 DQ10 D2 DQ9 E1 DQ8 E9 DQ7 D8 DQ6 D9 DQ5 C8 DQ4 C9 DQ3 B8 DQ2 B9 DQ1 A8 DQ0 Input/ Active Output High Data Input/Output
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Pin Configuration Table 4 F1 UDQM Input/Output Signals (cont'd) Polarity Function Active High -- Data Input/Output Mask Not Connected DQ Power Supply Input --
Pin Symbol Type E8 LDQM E2 NC A7 VDDQ B3 C7 D3 A3 VSSQ B7 C3 D7 A9 VDD E7 J9 A1 VSS E3 J1
Supply --
Supply --
DQ Ground
Supply --
Power Supply
Supply --
Ground
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HY[B/E]25L256160A[F/C]-7.5 256MBit Mobile-RAM
Functional Description
3
Functional Description
(BA[1:0] = 00B)
A10 A9 A8 A7 A6 A5 CL w A4 A3 BT w A2 A1 BL w A0
MR Mode Register Definition
BA1 0 BA0 0 A12 A11
MODE w
reg. addr
Field BL
Bits [2:0]
Type w
Description Burst Length Number of sequential bits per DQ related to one read/write command. Note: All other bit combinations are RESERVED. 000 001 010 011 111 1 2 4 8 full page (sequential burst type only)
BT
3
w
Burst Type See Table 5 for internal address sequence of low order address bits. 0 Sequential 1 Interleaved CAS Latency Note: All other bit combinations are RESERVED. 010 2 011 3
CL
[6:4]
w
MODE [12:7] w
Operating Mode Note: All other bit combinations are RESERVED. 000000 000100 Burst Read/Burst Write Burst Read/Single Write
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HY[B/E]25L256160A[F/C]-7.5 256MBit Mobile-RAM
Functional Description
Table 5 Burst Length 2 4
Burst Definition Starting Column Address A2 A1 A0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
8
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
Notes: 1. For a burst length of two, Ai-A1 selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, Ai-A2 selects the four-data-element block; A1-A0 selects the first access within the block. 3. For a burst length of eight, Ai-A3 selects the eight-data- element block; A2-A0 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
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HY[B/E]25L256160A[F/C]-7.5 256MBit Mobile-RAM
Functional Description
EMR Extended Mode Register Definition
BA1 1 BA0 0 A12 A11 A10 A9
(BA[1:0] = 10B)
A8 A7 A6 A5 A4 A3 A2 A1 PASR w A0
MODE w
TCSR w
reg. addr
Field PASR
Bits [2:0]
Type w
Description1) Partial Array Self Refresh 000 banks to be self refreshed: all 4 of 4 001 banks to be self refreshed: 2 of 4, BA[1:0] = 00B or 01B 010 banks to be self refreshed: 1 of 4, BA[1:0] = 00B 101 banks to be self refreshed: 0.5 of 4, BA[1:0] = 00B & RA12 = 0B 110 banks to be self refreshed: 0.25 of 4, BA[1:0] = 00B & RA[12:11] = 00B Temperature Compensated Self Refresh 00 on-chip temperature sensor enabled 01 Maximum case temperature: 45C, on-chip temperature sensor disabled 10 Maximum case temperature: 15C, on-chip temperature sensor disabled 11 Maximum case temperature: 85C, on-chip temperature sensor disabled Operating Mode 00h Normal operation
TCSR
[4:3]
w
MODE
[12:5]
w
1) All other bit combinations are RESERVED.
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Electrical Characteristics
4
4.1
Table 6 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. -- -- -- -- -- -- -- 50 max. -1.0 -1.0 -1.0 -1.0 -25 -55 -- -- Unit Note/ Test Condition
Voltage on I/O pins relative to VSS Voltage on I/O pins relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Case Temperature (extended) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current
VIN, VOUT VIN, VOUT VDD VDDQ TCASE TSTG PD IOUT
VDD + 0.5 V
+4.6 +4.6 +4.6 +85 +150 0.7 -- V V V C C W mA
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Table 7 Parameter Supply Voltage I/O Supply Voltage Supply Voltage I/O Supply Voltage Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Output High (Logic 1) Voltage Output Low (Logic 0) Voltage Input Leakage Current Recommended Operating Conditions and DC Characteristics1) Symbol min. Values max. +3.6 +3.6 0 0 V V V V V V V V A A
3)4) 3)4) 2)
Unit Note/ Test Condition
VDD VDDQ VSS VSSQ VIH VIL VOH VOL IIL
+2.3 +1.65 0 0 0.8 x VDDQ -0.3 -- -5
VDDQ + 0.3
+0.3 +0.2 +5
VDDQ - 0.2 --
IOH = -0.1 mA IOH = +0.1 mA
Any input 0 V VIN VDD; all other pins not under test VIN = 0 V DQ is disabled; 0 V VOUT VDDQ
Output Leakage Current IOZ -5 +5 1) 0 C TC 70 C (comm.) and -25 C TCASE +85 C 2) VDDQ < VDD + 0.3 V 3) All voltages referenced to VSS
4)
VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4 ns. VIL may undershoot to - 2.0 V for pulse width < 4 ns.
Pulse width measured at 50% points with amplitude measured peak to DC reference
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HY[B/E]25L256160A[F/C]-7.5 256MBit Mobile-RAM
Electrical Characteristics
Table 8 Parameter
Input and Output Capacitances Symbol min. Values typ. -- -- -- max. 3.5 3.8 5.0 pF pF pF -- -- 4.0 Unit Note/ Test Condition
1) 1)
1)
Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQ
CI1 CI2 CIO
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V 0.2 V, f = 1 MHz, TCASE = 25 C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
4.2
Table 9 Parameter Clock
Timing Characteristics
AC Timing Characteristics1)2) Symbol min. -7.5 max. 7.5 6 5.4 7.5 6 -- -- -- -- -- 133 125 105 -- -- -- -- -- 7.5 -- -- 100000 -- -- -- ns ns ns ns ns ns ns ns ns ns Unit Note/ Test Condition
DQ output access time from CLK
tAC3
-- -- --
tAC2
CK high-level width CK low-level width Clock cycle time
-- -- 2.5 2.5 7.5 8 9.5 -- -- -- 1.5 0.8 1.5 0.8 2 0 19 19 45 67 15 1
VDDQ < 2.3 V 3)4)5)8) VDDQ 2.3 V 3)4)5)8) VDDQ 3.0 V 3)4)5)8) VDDQ < 2.3 V 3)4)5)8) VDDQ 2.3 V 3)4)5)8)
- -
tCH tCL tCK3 tCK2 fCK3 fCK2
VDDQ 2.3 V 3) VDDQ < 2.3 V 3)
3)
Clock frequency
MHz VDDQ 2.3 V 3) MHz VDDQ < 2.3 V 3) MHz ns ns ns ns
3)
Setup and Hold Times Input setup time Input hold time CKE setup time CKE hold time Mode register setup time Power down moder entry time Common Parameters Active to Read or Write delay Precharge command period Active to Precharge command Active bank A to Active bank A period Active bank A to Active bank B delay CAS to CAS command delay
tIS tIH tCKS tCKH tRSC tSB tRCD tRP tRAS tRC tRRD tCCD
6) 6) 6) 6)
tCK
ns ns ns ns ns ns
7) 7) 7) 7) 7)
tCK
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HY[B/E]25L256160A[F/C]-7.5 256MBit Mobile-RAM
Electrical Characteristics Table 9 Parameter Refresh Cycle Refresh period Self refresh exit time Read Cycle Data output hold time Data output from high to low impedance Data output from low to high impedance DQM data output disable latency Write Cycle Write recovery time DQM write data mask latency 0 -- tCK 1) 0 C TC 70 C (comm.) and -25 C TCASE +85 C; recommended operating conditions unless otherwise noted
2) For proper power-up see the operation section of this data sheet. 3) Symbol index 2 and 3 refer to CL = 2 and CL = 3. 4) AC timing tests are referenced to the 0.9 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit (details will be defined later). Specified tAC and tOH parameters are measured with a 30 pF only, without any resistive termination and with a input signal of 1V/ns edge rate (see Figure 2). 5) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 7) These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) 8) Access time from clock tAC is 4.6 ns for -7.5 components with no termination and 0 pF load, Data out hold time tOH is 1.8 ns for -7.5 components with no termination and 0 pF load. 9) The write recovery time of tWR = 14 ns allows the use of one clock cycle for the write recovery time when the memory operation frequency is equal or less than 72MHz. For all memory operation frequencies higher than 72MHz two clock cycles for tWR are mandatory. QIMONDA recommends to use two clock cylces for the write recovery time in all applications.
AC Timing Characteristics1)2) (cont'd) Symbol min. -7.5 max. 64 -- -- -- 7 2 -- ms Unit Note/ Test Condition
tREF tSREX tOH tLZ tHZ tDQZ tWR tDQW
-- 1 3 1 3 -- 14
tCK
ns ns ns
4)7)8)
tCK
ns
9)
I/O 30 pF
Figure 2
Measurement Conditions for tAC and tOH
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HY[B/E]25L256160A[F/C]-7.5 256MBit Mobile-RAM
Electrical Characteristics
4.3
Table 10 Parameter
Current Specification
IDD Specification and Conditions1)2)
Symbol typ. -7.5 max. 65 0.6 20 3.5 25 80 155 mA mA mA mA mA mA mA A -- -- -- -- -- -- -- Unit Note/ Test Condition
Operating current Single bank access cycles Precharge standby current Power down mode Precharge standby current Non power down mode Non operating current Active state of 1 upto 4 banks, power down Non operating current Active state of 1 upto 4 banks, non power down Burst operating current Read command cycling Auto refresh current Auto refresh command cycling Self refresh current
IDD1 IDD2P IDD2N IDD3P IDD3N IDD4 IDD5 IDD6
tRC = tRC,MIN 3)
CS = VIH,MIN, CKE VIL,MAX 3) CS = VIH,MIN, CKE VIH,MIN 3) CS = VIH,MIN, CKE VIL,MAX 3) CS = VIH,MIN, CKE VIH,MIN 3)
3)4)
tRC = tRC,MIN tCK =infinity,
CKE = 0.2 V
see Table 11
Deep power down mode current IDD7 -- 5 A 1) 0 C TC 70 C (comm.) and -25 C TCASE +85 C; recommended operating conditions unless otherwise noted
2) For proper power-up see the operation section of this data sheet. 3) These parameters depend on the frequency. These values are measured at 133MHz for -7.5 and at 100MHz for -8 parts. Input signals are changed once during tCK. If the devices are operating at a frequency less than the maximum operation frequency, these current values are reduced. 4) These parameters are measured with continuous data stream during read access and all DQs toggling. CL = 3 and BL = 4 is used and the VDDQ current is excluded.
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Electrical Characteristics
Table 11 Parameter
IDD6 Programmable Self Refresh Current1)2)
Symbol -8 max. t.b.d. 250 475 725 t.b.d. 150 250 450 t.b.d. 100 150 275 Unit TCASE TCSR A A A A A A A A A A A A
3)
Note/ Test Condition
Self refresh current Self refresh mode, full array activations = all banks
IDD6
max. 15C max. 45C max. 70C max. 85C max. 15C max. 45C max. 70C max. 85C max. 15C max. 45C max. 70C max. 85C
tCK =infinity,
CKE = 0.2 V 4)
Self refresh current IDD6 Self refresh mode, half array activations = bank 0 + 1 Self refresh current IDD6 Self refresh mode, quarter array activations = bank 0
1) 2) 3) 4)
tCK =infinity,
CKE = 0.2 V 4)
tCK =infinity,
CKE = 0.2 V 4)
Recommended operating conditions unless otherwise noted. For proper power-up see the operation section of this data sheet. Extended Mode Register A4-A3. Target values to be verified on final product and may change.
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Package Outline
5
Package Outline
P-TFBGA-54 (Plastic Thin Small Outline Package Type II)
tolerance 0.1mm for length and width Figure 3 Package Outline
You can find all of our packages, sorts of packing and others in our Qimonda Internet Page: http://www.qimonda.com. SMD = Surface Mounted Device
Internet Data Sheet 16
Dimensions in mm
Rev. 1.41, 2006-12 04292004-EQNL-FLNW
HY[B/E]25L256160A[F/C]-7.5 256MBit Mobile-RAM
Table of Contents
1 1.1 1.2 2 3 4 4.1 4.2 4.3 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 14
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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Internet Data Sheet
Edition 2006-12 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in 1. Any applications that are intended for military usage (including but not limited to weaponry), or 2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or (ii) Cause the failure of such Critical Systems; or b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or (ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com

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